Main articles: CPU cache and cache
Small memories on or near the CPU can run faster than main memory much more important. Most processors since the 1980s have used one or more caches, sometimes cascading; High-end modern embedded microprocessors, desktop and server can have up to six types of coverage (between levels and functions). Examples of covers with a specific function are cache D and cache I and lookaside buffer translation of the MMU.
Graphics processing units (GPUs) often display texture read caches previously only limited and introduced swizzled textures to improve consistency of the 2D cache. Cache errors significantly affect performance, eg. Eg if mipmapping was not used. Caching was important to take advantage of 32-bit (and wider) transfers for texture data that were often as little as 4 bits per pixel, indexed in complex models by means of arbitrary UV coordinates and perspective transformations in The reverse texture mapping.
Gradually, as the GPU discusses (especially with GPGPU computing shaders), they developed progressively larger and more general caches, including instruction cache shaders, which feature features increasingly common with CPU caches. For example, the architecture of the GT200 GPU does not have an L2 cache, while the Fermi GPU had 768 KB of last level cache, the Kepler GPU in 1536 KB of last level cache and the Maxwell 2048 KB GPU Last -level cache. These caches have become able to handle the synchronization primitives between threads and atomic operations, and the interface with a type of MMU processor.
Digital signal processors were also extended over time. Previous designs use a pen-memory powered by DMA, but modern DSP such as Qualcomm Hexagon often include a set of very similar caches on a CPU (for example, a modified Harvard architecture with L2 shared split L1 cache and D leathers).
Main article: lookaside buffer Translation
A memory management unit (MMU), which extracts entries from the page table from main memory has a specialized cache, which is used to record the results of a virtual address to physical address translations. This specialized cache is called research buffer translation (TLB).