There is an inherent balance between size and speed (taking into account that more resources imply greater physical distances), but also a compromise between expensive technology and premium (SRAM, for example) Disks).

The buffer supplied by a cache benefits both performance and latency:

Greater resource causes significant latency with access – for example. It can take 100s of clock cycles for a modern 4GHz processor to reach the DRAM. This is mitigated by reading in large chunks, hoping that these readings will be from other regions. Prediction or explicit prior obtaining could also guess where future readings will come and place orders in advance; If done correctly, latency is omitted altogether.

Speed ​​and granularity
The use of cache also allows for greater performance of the underlying resource, combining several testa transfers in a higher demand and more efficient. In the case of DRAM, it can be served by a larger bus. Imagine a byte-detection program in a 32-bit address space, but being served by a 128-bit off-chip data bus; Individual access to the unencrypted bytes would use 1/16 of the total bandwidth, and 80% of the data movement would be handled. Reading the larger blocks reduces the fraction of the bandwidth required to transmit the address information.