The hardware implements the cache as a memory block for the temporary storage of data that can be used again. CPU processing (CPU) and disk drives (HDD) often use a cache, such as browsers and web servers.

A cache consists of a set of entries. Each entry has associated data, which are copies of the same data in a backup store. Each entry also has a tag that specifies the identity of the data in the backup store of which the entry is a copy.

When the client cache (CPU, Internet browser, operating system) needs to access data is supposed to exist in the backup store, the cache is first checked. If an entry can be found with a label matches that of the desired data, the input data is used instead. This situation is known as the “cache hit”. For example, an Internet browser program can check its local cache on the disk to see if it has a local copy of the contents of a Web page to a specific URL. In this example, the URL is the tag, and the content of the web page corresponding to the data. The percentage of access that results in cache hits is known as the name success rate or cache hit rate.

The alternative situation, when the cache is queried and checked for missing data with the desired tag, came to be known as a cache error. Previously non-failed data extracts from the backup store for handling the missing are usually copied into the cache, ready for the next access.

During an error cache, the processor typically ejects another entry to make room for previously unreached data. The heuristic used to select the entry to be expelled is known as the name of the replacement policy. A popular, “least recently used” (LRU) replacement policy replaces the least recently used entry (see cache algorithm). More efficient caches calculate according to the frequency of use in the size of the stored contents, as well as the latencies and speeds of the cache and the backup store. This works well for large amounts of data, longer latencies and slower rates, such as experience with a hard drive and the Internet, but is not effective for use with a CPU cache.